Expertise in developing complex Analog and Mixed Signal IP’s from scratch as well as design modifications.

Cerium Design Team has experienced in developing IP’s for high speed serial interfaces, high performance applications etc.

Expertise in developing state of the art mixed signal verification environments for complex mixed signal IPs.

Cerium Layout team has extensive experience in high speed and core analog layout. We have proven experience in 14nm (Finfet), 10nm (Finfet) and 7nm (Finfet) process nodes.

Cerium systems has more than 10 years of experience in technology nodes from 0.25um to 7nm where team demonstrated for maximum density and high routing performances. Our team has been developing the following standard cells like Inverters, Buffers, Clock cells, NAND, NOR, AND, OR, AOI, OAI, AO, OA, XNOR, XOR, MUX, IMUX, D-Latch, D-Flops, Scan D-Flops, Half-Adders, Full-Adder cells. Also experienced to hand power management, retention and special operation cells for the specific application support. Our team has the following design cycle supported for many of our customer’s library developments.

Cerium Systems has highly focused design and layout engineers to develop FinFET memory cells. Team handled latest process technology likes 14nm and 7nm for the various foundries. Our team has highly experienced of advanced custom circuit implementations. Also developed good understanding of SRAM Architecture , circuit design, physical implementation, compiler automation, characterization, timing and model generations. Team has direct experience with most of the advanced technology nodes and interfaced with silicon validation.